Here is a story of industrial policy done the boring, patient way—with clear incentives, a single-window institution, and a bias for getting shovels in the ground before grandstanding about nanometres. India’s semiconductor push, housed in the India Semiconductor Mission (ISM), is not some misty aspiration but a layered programme that starts where the global supply chain will let a new entrant start—assembly, test and packaging; power and sensor chips; display manufacturing—and then climbs the stack to full-fledged wafer fabs. The political bet is straightforward: give uniform, predictable fiscal support and remove transaction friction, then pair it with demand, skills and diplomatic ballast. The modified Semicon India programme does exactly that—offering 50% of project cost as fiscal support, on a pari-passu basis, across silicon fabs, display fabs, compound semiconductors and ATMP/OSAT. In a world of balkanised chip geopolitics, this is among the most generous public matches on offer, and it is simple enough for investors to underwrite.
What turns the policy from subsidy to strategy is the decision to build the design base in parallel. The Design Linked Incentive (DLI) scheme funds Indian fabless projects and, crucially, provides access to expensive EDA toolchains; by August 2025 the government said 23 chip-design projects had been sanctioned and 72 companies had secured EDA access—small numbers by Taiwanese standards, but the beginnings of a pipeline India long lacked. A country that already designs for the world in software is learning to tape-out at home, not just write firmware. That, paired with ISM’s MoUs with the US, EU, Japan and Singapore, creates technology and talent corridors instead of one-off press releases.
Implementation, not intent, is what once tripped India. This time the milestones are more tangible. Micron’s ATMP mega-site at Sanand crossed cleanroom validation this summer, the sort of dull, vital step that separates factory PowerPoints from production lines. In Assam, Tata’s TSAT project is planned as a high-volume packaging hub, while CG Power with Renesas and Stars Microelectronics has inaugurated a pilot line in Sanand. And on the front that captures headlines, Tata’s greenfield fab at Dholera—backstopped by the 50% support—has broken ground to target mature-node output first, with capacity scaled to demand rather than vanity. Gujarat, for its part, is even building worker housing around the fab zone: industrial policy conceived as an ecosystem, not a ribbon-cutting.
The scaffolding under all this is equally deliberate. ISM sits as the nodal agency, trimming permit cycles and aligning state-level sops with central incentives. Upstream, the SPECS scheme adds a 25% capital subsidy for the less glamorous but utterly necessary inputs—chemicals and gases, cleanroom kit, capital equipment, even engineering for semiconductor tools. Downstream, public procurement is being marshalled for “demand aggregation,” nudging railways, power utilities and defence to specify India-made chips where reliability, not bleeding-edge geometry, matters most. This is how nations accumulate know-how: through repetitive, boring orders that let suppliers climb the yield curve.
The talent piece—often an afterthought—has been hauled forward in the queue. AICTE has rolled out VLSI manufacturing curricula; the Chips-to-Startup programme is training tens of thousands at over a hundred institutions; Lam Research’s Semiverse tie-up with IISc, IBM collaborations and Purdue partnerships are creating lab access and internships. These are not yet the elite apprenticeship foundries of Hsinchu, but they are a credible start to move Indian engineers from verification and systems work to process integration and yield engineering—the muscle memory fabs truly need.
To be sure, realism beats triumphalism. India will not be shipping 3-nanometre smartphones in two years; it doesn’t need to. Mature nodes around 28–65 nm still power cars, power grids, industrial controls and telecom gear. Packaging is becoming a profit centre as 2.5D/3D integration spreads, and compound semiconductors—SiC and GaN—sit at the heart of EVs and renewables. By subsidising these segments at the same 50% clip as CMOS fabs, India is anchoring itself where global demand is deepest and geopolitics is least hostile. If execution continues—permits predictable, power and water reliable, customs swift—the country’s first wave of factories will find customers at home and abroad, and the second wave will have bankers willing to bet on depreciation schedules measured in decades, not electoral cycles.
The next moves should remain gloriously unglamorous: lock in long-term offtake from public buyers; publish fab-grade service-level metrics for utilities and logistics; expand SPECS-style support to specialty gases and targets; keep DLI’s cohort competitive by tying grants to taped-out silicon and first revenue. And then keep showing the pictures that matter: not ministers at conferences, but operators in bunny suits, pallets at goods-in, and SPC charts inching toward six sigma. For once, India’s semiconductor vision is framed less as a moon-shot than as a factory-shift. That modesty may be its sharpest competitive edge.
- “50% fiscal support, across the stack—fabs, displays, compounds, ATMP—has turned intent into investible projects.”
- “Design isn’t an afterthought: 23 DLI-backed projects and 72 firms on EDA tools seed a domestic fabless pipeline.”
- “Execution, not hype: Micron’s cleanroom validated; Tata’s Dholera fab breaks ground; packaging ramps in Assam and Sanand.”
- “SPECS’ 25% capital support funds the unsexy kit—chemicals, tools, cleanrooms—that make fabs actually run.”
- “Talent as infrastructure: C2S, new VLSI curricula, and ISM’s global MoUs push engineers from code to cleanrooms.”